Senior ASIC FPGA Development And Verification Engineers

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Position Overview:

Boeing Defense Space & Security seeks Senior ASIC FPGA Development and Verification Engineers (level 5) to support the Satellite Capabilities organization and multiple product lines based in El Segundo, CA. Join this diverse team and lead all aspects of the block to top design and verification activities from inception to silicon realization. Work on ambitious and leading edge technology nodes and SOC designs in a fast paced and supporting team oriented space.

Contribute to the solutions that form the heart of Boeing’s products. Leverage and benefit from the best tools industry has to offer, implement your ideas and see them come to life in hardware. You will grow a diverse set of skills and help the people on your team reach their full potential.

Position Responsibilities:

• Architects, implements, and verifies digital as well as mixed signal solutions. Designs custom IP, as well as uses innovative commercial IP and VIP across the ASIC and FPGA domains. Structures high-level architectural documentation and develops detailed implementation and verification approaches, implements in SystemVerilog and verifies within a team environment, using UVM.

• Maintains detailed requirements and specifications for various electronic products.

• Develops and leads detailed designs that are groundbreaking and sophisticated in scope.

• Conducts various methods of testing and analysis to support design and verification.

• Provides in-depth engineering support throughout the lifecycle of the product.

• Conducts trade studies and literature research to support future product designs and methods.

• Works independently and leads teams under minimal direction of a department manager.

This position allows part-time telecommuting. The selected candidate will be required to perform work onsite at the El Segundo, CA location.

This position must meet Export Control compliance requirements, therefore a “US Person” as defined by 22 C.F.R. § 120.15 is required. “US Person” includes US Citizen, lawful permanent resident, refugee, or asylee

Basic Qualifications (Required Skills and Experience):

• Bachelor, Master or Doctorate of Science degree from an accredited course of study, in engineering, computer science, mathematics, physics or chemistry

• Fifteen (15) or more years of experience in Digital ASIC/FPGA design or verification.

• Seven (7) or more years of work experience using Verilog or SystemVerilog.

Preferred Qualifications (Desired Skills/Experience):

• Bachelor's degree and 20 or more years' experience in digital ASIC/FPGA design and verification, Master's degree with 15 or more years' experience in digital design/verification, or PhD degree with 10 or more years’ experience in digital design/verification.

• Work experience Universal Verification Methodology (UVM) bench implementation, start-to-finish.

• Experience using scripting languages: Make, Perl, Python, shell scripts, etc.

• Experience using Revision Control Systems: Subversion (SVN), CVS, Git.

• Work experience writing requirements specification documents.

• Work experience writing architectural design documents (micro-architecture documents with timing diagrams, detailed design blocks, etc.).

• Work experience performing RTL synthesis.

• Work experience performing Static Timing Analysis and correcting timing violations.

• Work experience simulating a digital design using hardware verification languages: SystemVerilog and SystemVerilog Assertions.

• Work experience using Object Oriented Programming concepts: Inheritance, Polymorphism, etc.

• Educational or work experience using object oriented programming (OOP), e.g. Java, C++.

Typical Education and Experience:

Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, computer science, mathematics, physics or chemistry (e.g. Bachelor) and typically 14 or more years' related work experience or an equivalent combination of technical education and experience (e.g. PhD+9 years' related work experience, Master+12 years' related work experience). In the USA, ABET accreditation is the preferred, although not required, accreditation standard.

**Relocation:

This position offers relocation based on candidate eligibility.

Drug Free Workplace

Boeing is a Drug Free Workplace where post offer applicants and employees are subject to testing for marijuana, cocaine, opioids, amphetamines, PCP, and alcohol when criteria is met as outlined in our policies.

Shift:

This position is for 1st shift.

Eligible for 3ERP

Equal Opportunity Employer:

Boeing is an Equal Opportunity Employer. Employment decisions are made without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, physical or mental disability, genetic factors, military/veteran status or other characteristics protected by law.