Principal FPGA Engineer

Principal Engineer
Engineer Principal – FPGA Design

What You'll Do

• Design digital hardware including FPGA development for space-based, high reliability electronic systems. Assignments include designs which will include SOC architectures utilizing soft-core processors, digital filters, image processing algorithms, and communication interfaces/protocols.
• Design and implement test fixtures including test plans for both chip-level and board level environments and create reusable circuits that can be utilized across multiple projects.
• Maintain a regular and predictable work schedule.
• Establish and maintain effective working relationships within the department, the Strategic Business Units, Strategic Support Units and the Company. Interact appropriately with others in order to maintain a positive and productive work environment.
• Perform other duties as necessary.

What You'll Need

• BS degree or higher in Engineering or a related technical field is required plus 12 or more years related experience.
• Each higher-level degree, i.e., Master’s Degree or Ph.D., may substitute for two years of experience. Related technical experience may be considered in lieu of education. Degree must be from a university, college, or school which is accredited by an agency recognized by the US Secretary of Education, US Department of Education.
• Digital system partitioning and advanced function implementation in FPGAs. Strong design, documentation and implementation of high-speed digital electronics, FPGAs, and embedded processor systems are desired.
• Strong electronic circuit design and electronic systems background.
• Strong FPGA and board design skills.
• Expertise in VHDL/Verilog, System Verilog and OVM/UVM, and Modelsim/Questa simulator is a plus.
• Experience in developing specifications, cost, schedule, and resource requirements for digital/FPGA designs.
• Familiarity with cPCI, Ethernet, DSP, 1553, VPX, Spacewire or Firewire is a plus.
• Familiarity with Mentor Graphics DxD, Hyperlynx for schematic design and SI analysis is a plus.
• Ability to work requirements and flow down for system/subsystem/box/board needs.
• Knowledge of space radiation effects is a plus.
• Familiarity with ASIC tools, libraries, design flow and fabrication is a plus.
• Space or military experience highly desired, but not required.
• Ability to obtain and maintain a security clearance is required.
• Good verbal and written communication skills, as well as strong presentation skills.

Working Conditions

• Work is performed in an office, laboratory, production floor, or clean room, outdoors or remote research environment.
• May occasionally work in production work centers where use of protective equipment and gear is required.
• May access other facilities in various weather conditions.
• Travel and local commute between Ball campuses and other possible non-Ball locations may be required.

A current DoD clearance and/or SCI access with Polygraph is not required to be eligible for this position, however applicant must be willing and eligible for submission within 60-90 days after an offer is accepted and must be able to maintain the applicable clearance/access. By applying to this position, you are agreeing to complete a National Security Clearance Pre-Screen Questionnaire to evaluate your general ability to obtain the required security clearance or government customer access associated with this position.

· Relocation for this position is available.

What are the 3-4 non-negotiable requirements of this position?

Related BS or higher and 12+ years of related experience, US citizenship required, digital system partitioning and advanced function implementation in FPGA's required.
Related keywords: software engineer, mechanical engineer, engineer

Job Type: Full-time

Pay: $142,000.00 - $179,000.00 per year

Benefits:

• 401(k)
• Health insurance
• Paid time off

Schedule:

• Monday to Friday

Education:

• Master's (Preferred)

Visa Sponsorship Potentially Available:

• No: Not providing sponsorship for this job

Work Remotely:

• Temporarily due to COVID-19