ASIC Design Verification Senior Staff Engineer

As part of Accenture’s Industry X, the Silicon Design group is a diverse team of world class silicon engineers. We have 100+ years of cumulative hands on experience in architecture, logic design, verification, physical design, emulation and firmware . We use the latest silicon technologies and processes to help our clients create well-designed solutions to highly complex challenges. We are designing and developing next-generation, high performance SoCs, supporting our clients in their drive to deliver their product vision to their users. We are involved in all aspects of chip design from definition and architecture through to verification and signoff. Accenture engineers are true “Silicon to SW” Partners, allowing a new breed of companies in the semiconductor ecosystem to innovate in an unparalleled time to market. Whether at our Silicon Design Center in Phoenix or at one of our other locations you will get to collaborate and innovate with the world’s leading product development companies. In our dynamic fast-paced environment you will get to make the impossible possible. Accenture is invested in our team member’s growth and provide many opportunities for training and skills expansion. We are looking for SoC Design Verification Engineer to provide design verification services for multi CPU/DSP SoC. Responsibilities:

• Testbench development - System Verilog UVM and C tests
• Integration/development of C tests/APIs and SW build flow
• Integration/development of UVM mailboxes and HW/SW communication components
• Integration of lower level UVM testbenches
• Test plan development
• Power Aware testbench development and simulations
• Seamless porting between simulation/emulation/prototyping platforms
• Regression setup and debug for RTL/Gate Level Netlist/UPF PA sim/Emulation/Proto
• Coverage collection and closure
• Working with cross functional teams (DV/Arch/Design/FW) to identify coverage scope

Racking up those air miles will have to wait, as weekly non-essential travel to client sites Monday through Thursday is currently suspended. For now, all Accenture business travel, international and domestic, is currently restricted to client-essential sales/delivery activity only.

Please note: The safety and well-being of our people continues to be the top priority, and our decisions around travel are informed by government COVID-19 response directives, recommendations from leading health authorities and guidance from a number of infectious disease experts.

Basic Qualifications:

• Bachelor’s Degree or equivalent (12 years) work experience (If an, Associate’s Degree with 6 years of work experience)
• 7+ years of experience in RTL Design and Verification area of which 5+ years of experience in SoC Design Verification and HW/SW verification

Preferred Qualifications:

• Deep knowledge of System Verilog UVM and vertical testbench integration
• Knowledge of low level HW/SW interaction and debug
• Knowledge of multi CPU and debug architectures
• Experience with development of fully automated flows
• Experience with low level SW debug - disasm, Tarmac, trace
• Experience with coresight architecture
• Experience with embedded SW low level concepts and debug - Tarmac, ROM, RAM, linkers, elf, disasm, code sections, cache, security
• Experience with coverage merging across simulation and emulation
• Experience with Power Aware and Gate Level Netlist in Emulation
• Experience with development of fully automated flows
• Experience with Gate Level Simulations
• Python Scripting

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